1. Field of the Invention
The present invention relates to a line memory, and more particularly to a line memory which is used when signal processing is performed, for example, in a television set (TV) or a video tape recorder (VTR) by using a correlation between a current line and a preceding line.
2. Description of Related Art
A line memory is used in a signal processing in which a correlation between a current line and a preceding line is, for example, used to demultiplex a digitized composite video signal to a luminance signal and color signals (this is called YC demultiplexing) in TV or VTR.
In case of National Television System Committee (NTSC) system and a signal processing frequency of 4 fsc (about 14.3 MHz. Hereinafter called a clock CLK. fsc: color sub-carrier frequency, 1 fsc=3.579545 MHz), a memory capacity required for a line memory is 910 words (1 word=8 bits) in an example case where a resolution of 1 dot is 8 bits and the number of dots in one line is 910 dots.
FIG. 8 is a block diagram showing the configuration of a conventional line memory.
In FIG. 8, 50 indicates a memory, having a capacity of 910 words (1 word=8 bits), for storing a line of dot data LDT. 51 indicates a read/write address counter operated according to a clock (8 fsc. Hereinafter called a double clock 2CLK) having a frequency which is double of the clock CLK (4 fsc). 52 indicates a read/write control unit for producing an address signal 63, a read enable signal 62 and a write enable signal 64 according to a read/write address signal 61 output from the read/write address counter 51 and controlling a data reading-out from the memory 50 and a data writing-in to the memory 50.
53 indicates a write register for delaying dot data LDT of a current line by one time-period of the double clock 2CLK and outputting the delayed dot data LDT as write register data 65. 54 indicates a read register for delaying dot data of a preceding line read out from the memory 50 by one time-period of the double clock 2CLK and outputting the delayed dot data as read register data 66. 55 indicates a flip-flop for delaying the dot data LDT of the current line by one time-period of the clock CLK and outputting the delayed dot data LDT as dot data 67. 56 indicates an arithmetic processing unit for receiving both the dot data 67 of the current line and the read register data 66 of the preceding line and performing a prescribed picture processing.
Next, an operation is described.
FIG. 9 is a time chart showing an operation of each unit of the conventional line memory.
In a first time-period T1 of the double clock 2CLK, a reset signal (not shown) is received in the read/write address counter 51 to initialize the read/write address counter 51, an initial value of 38DH (H indicates that 38DH is a hexadecimal number, and 38DH is equivalent to 909 expressed by a decimal number) is set, and the initial value is output as a read/write address signal 61. In the read/write control unit 52, a read enable signal 62 is produced from the read/write address signal 61 which specifies the initial value of 38DH (909), the read enable signal 62 is output to the memory 50 with an address signal 63 of 38DH (909), and dot data A1 of a first line is read out from the memory 50. Thereafter, in a second time-period T2 of the double clock 2CLK, the dot data A1 is output through the read register 54 as read register data 66. Also, the read register data 66 and dot data 67, which is obtained by delaying dot data LDT in the flip-flop 55 by one time-period of the clock CLK, are input to the arithmetic processing unit 56, and a desired picture processing is performed.
In the second time-period T2 of the double clock 2CLK, a write enable signal 64 is produced from the read/write address signal 61, the write enable signal 64 is output to the memory 50 with the address signal 63 of 38DH (909), and write register data 65, which is obtained by delaying dot data LDT in the write register 53 by one time-period of the double clock 2CLK and denotes dot data B1 of a second line, is written in the memory 50. Thereafter, in a next time-period T3 of the double clock 2CLK, a count down operation is performed in the read/write address counter 51, a read/write address signal 61 of 38CH (908) is output from the read/write address counter 51, and the data reading-out from the memory 50 and the data writing-in to the memory 50 are performed in the same manner as the above-described operation. In a following operation, the data reading-out and the data writing-in are alternately performed for each time-period of the clock CLK (4 fsc) while decreasing a counted value of the read/write address counter 51 one by one.
Also, when the counted value is counted down to 0H (0) in the read/write address counter 51, the reading-out of the dot data of the first line and the writing-in of the dot data of the second line are completed, and the reading-out of the dot data of the second line and the writing-in of dot data of a third line are successively performed. Thereafter, in the same manner, the reading-out of dot data of a preceding line and the writing-in of dot data of a current line are performed one after another.
However, because the conventional line memory has the above-described configuration, in the signal processing using the line memory, it is required to perform both the reading-out of the dot data of the preceding line stored in the memory 50 and the writing-in of the dot data of the current line to the memory 50 within one processing time-period (1/(4 fsc)=about 70 ns). Therefore, it is required to set an operating speed of a random access memory (RAM) used in the memory 50 to a speed (8 fsc) double of the signal processing frequency, that is, a signal processing time-period equivalent to xc2xd (1/(8 fsc)=about 35 ns) of one processing time-period for the signal processing. That is, there is a problem that a RAM operable at high speed has to be used. Also, this high speed type RAM is expensive so as to heighten a cost of the memory 50, and there is another problem that a picture processing apparatus using this high speed type RAM is expensive.
An object of the present invention is to provide, with due consideration to the problems of the conventional line memory, a line memory in which a RAM obtained at a low cost and operable at low speed is used.
The object is achieved by the provision of a line memory comprising first and second memories respectively having a memory capacity which is half of a memory capacity required to store all pieces of dot data of one line, read address producing means for producing a read address signal to be used to read out the dot data for each dot, write address producing means for producing a write address signal to be used to write the dot data for each dot, and a memory access signal producing unit for performing, for each time-period of a reading-out or a writing-in, both the production of an address signal, which specifies an address of the first memory or the second memory, and a read enable signal, which is used to alternately read out dot data of a preceding line stored in the first memory or the second memory, according to the read address signal produced by the read address producing means and the production of an address signal, which specifies an address of the second memory or the first memory, and a write enable signal, which is used to alternately write dot data of a current line stored in the second memory or the first memory, according to the write address signal produced by the write address producing means. In this line memory according to the present invention, both the reading-out of the dot data of the preceding line stored in the first memory or the second memory and the writing-in of the dot data of the current line to the second memory or the first memory are performed in the same time-period.
Therefore, the line memory can be operated according to a clock CLK of which a signal processing frequency is 4 fsc, a double clock 2CLK having a frequency, which is double of the clock CLK, is not required, and the line memory, in which the memories operable at a low speed and obtained at a low cost, can be obtained.
Also, in the line memory according to the present invention, it is preferred that the dot data of the preceding line is read out from a storing area of a specified address of the first memory or the second memory in a first time-period of the reading-out or the writing-in, and the dot data of the current line is written in the storing area of the address of the first memory or the second memory in a second time-period.
Therefore, the line memory can be operated according to a clock CLK of which a signal processing frequency is 4 fsc, a double clock 2CLK having a frequency, which is double of the clock CLK, is not required, and the line memory, in which the memories operable at a low speed and obtained at a low cost, can be obtained.
The object is also achieved by the provision of a line memory comprising first and second memories respectively having a redundant memory capacity of at least one piece of dot data in addition to a memory capacity which is half of a memory capacity required to store all pieces of dot data of one line, read address producing means for producing a read address signal to be used to read out the dot data for each dot, write address producing means for producing a write address signal to be used to write the dot data for each dot, and a memory access signal producing unit for performing, for each time-period of a reading-out or a writing-in, both the production of an address signal, which specifies an address of the first memory or the second memory, and a read enable signal, which is used to alternately read out dot data of a preceding line stored in the first memory or the second memory, according to the read address signal produced by the read address producing means and the production of an address signal, which specifies an address of the second memory or the first memory, and a write enable signal, which is used to alternately write dot data of a current line stored in the second memory or the first memory, according to the write address signal produced by the write address producing means. In this line memory according to the present invention, the address signal produced according to the write address signal in the memory access signal producing unit specifies either an address of an area of the second memory or the first memory, in which no dot data of the preceding line is stored, or an address of the second memory or the first memory which is set to a non-stored state by reading out the dot data of the preceding line, and both the reading-out of the dot data of the preceding line stored in the first memory or the second memory and the writing-in of the dot data of the current line to the second memory or the first memory are performed in the same time-period.
Therefore, the line memory can be operated according to a clock CLK of which a signal processing frequency is 4 fsc, a double clock 2CLK having a frequency, which is double of the clock CLK, is not required, and the line memory, in which the memories operable at a low speed and obtained at a low cost, can be obtained.
Also, in the line memory according to the present invention, it is preferred that a difference between the read address signal produced by the read address producing means and the write address signal produced by the write address producing means in the same time-period is an odd number.
Therefore, the line memory can be operated according to a clock CLK of which a signal processing frequency is 4 fsc, a double clock 2CLK having a frequency, which is double of the clock CLK, is not required, and the line memory, in which the memories operable at a low speed and obtained at a low cost, can be obtained.